1. Field of the Invention
The present invention relates to an erasing method and an erasing device for a non-volatile semiconductor memory on the basis of a channel erasing system.
2. Description of the Prior Art
A gate/source erasing system and a channel erasing system are known erasing systems for a non-volatile semiconductor memory. The gate/source erasing system is disclosed in, for example, U.S. Pat. No. 5,077,691,. Briefly, according to the gate/source erasing system, an erasing operation is performed by applying a negative voltage to the gate of a memory cell while applying a positive voltage to the source of the memory cell and keeping the drain of the memory cell opened at the erasing time.
FIG. 13 shows the structure of a memory cell which is suitable for the gate/source erasing system. As shown in FIG. 13, drain D is formed on a P-type substrate P-sub on the basis of an N.sup.+ -diffusion layer, and source S is formed on the P-type substrate on the basis of an N.sup.- diffusion layer and an N.sup.+ diffusion layer. Floating gate FG and control gate CG are formed on this substrate. In the gate/source erasing type memory cell as mentioned above, an interband tunnel current flows from the source S to the substrate P-sub, and thus the current consumption is large. Further, a high withstanding voltage structure is indispensable to the source S, so that a special manufacturing step of forming the junction of the source diffusion layer deeply is necessary, and a restriction is imposed on minimum gate size.
The channel erasing system can solve the aforementioned problem of the gate/source erasing system, and FIG. 14 shows the structure of the memory cell which is suitable for the channel erasing system. In this memory, drain D based on an N.sup.+ diffusion layer and source S based on a N.sup.+ diffusion layer are formed on a P-type substrate P-sub. On the substrate are formed floating gate FG and control gate CG. In such a channel erasing type memory cell, no high electric field is applied to the source S, and thus the source S may be designed in the same structure as the drain D. Further, when the effective channel length Leff is set to the same as shown in FIG. 13, the dimension of each gate can be reduced, and thus this is effective to reduce the size of the memory cell.
Next, the channel erasing system will be briefly explained with reference to FIGS. 15 and 16.
FIG. 15 shows a system (hereinafter referred to as "first system") in which the drain and source of the memory cell are kept open and a negative voltage of -13 (V) is applied to the gate of the memory cell while a positive voltage of 5(V) is applied to the substrate portion. Such a system is disclosed in "A 5-V-Only 16-Mb Flash Memory with Sector Erase Mode" of IEEE JOURNAL OF SOLID-STATE CIRCUITS, pp1547-1554 VOL. 27. NO. 11 NOVEMBER 1992.
FIG. 16 shows a system (hereinafter referred to as "second system") in which a positive voltage of 3(V) is applied to the drain and source of the memory cell, a negative voltage of -15(V) is applied to the gate of the memory cell and a positive voltage of 3(V) is applied to the substrate portion. Such a system is disclosed in "Low Voltage NVGTM: A New High Performance 3V/5V Flash Technology for Portable Computing and Telecommunications Applications" of IEEE TRANSACTION ON ELECTRON DEVICES, pp1510-1517, VOL. 43. NO.9 SEPTEMBER 1996.
In the first system, the problem of the gate/source erasing system is avoided, however, it has an unstable erasing characteristic because the source/drain of the memory cell is kept open and thus the source/drain may be set to a higher voltage than the substrate of the memory cell due to the fluctuation of a power source or the like.
On the other hand, in the second system, the problems of the gate/source erasing system and the first system are avoided. However, circuits for applying a voltage to the source and drain of the memory cell respectively are needed, and particularly the circuit for applying the voltage to the drain has a large overhead.